１ECTCの紹介と最近の研究動向、および用語の説明

11 ECTCの発表件数の推移や国別／研究機関別投稿状況

12 先端半導体パッケージングの分類や動向

13 ハイブリッド接合の概要

14 Co-Packaged Optics (CPO)の概要

２ハイブリッド接合と光電融合以外の注目論文 10件

Session 1: Enabling Fan-In and Fan-Out Wafer/Panel Level Packaging Technology

・Paper 1. A Novel 600mm Panel Interposer with 300mm Panel Assembly Approach for Advanced Packaging

Solution in HPC and AI Applications

(ASE)

Session 7: Heterogeneous Integration: The New Horizons

・Paper 1. Scaling the EMIB-T Advanced Packaging Technology to Address the Future HPC/AI Demand

(Intel)

Session 10: Reliability of Large Body High Performance Computing and AI Packaging Solutions

・Paper 3. The First Report of Si Bridge Type 2.5D Package Reliability for Automotive Applications

(Socionext;, Renesas Electronics & MIRISE)

Session 13:

Advances in Thermal Design and Characterization

・Paper 1. Process Development and Thermal Characterization of Micropillar Direct-to-Silicon Liquid Cooling

Solution on CoWoS-R Platform

(TSMC)

Session 14:

RDL and Fan-Out Interconnections

・Paper 2. Panel CMP Co-Planarization of Heterogeneous Interfaces for Damascene Organic RDL Interposers (L/S = 2/2μm)

(Resonac)

Session 16: Assembly and Manufacturing: 3D Stacking and Thermal Solutions

・Paper 2. First Demonstration of μBump-Based Massive Orthogonal Stacking Assembly IC (MOSAIC) Cube for

SoC-DRAM Direct

(The University of Tokyo and Tohoku University)

Session 19: Substrate Core Innovations: Glass, Ceramic, and Silicon

・Paper 2. Glass Core Substrates – Next Generation Advanced Packaging Platform for AI and HPC

(Intel)

Session 29: Innovation in Metallization, Alignment, Additive Manufacturing, and Low Temperature

Interconnection

・Paper 5. Metallization Challenges: Conformable Deposition for Super High-Aspect Ratio (> 100) Fine TGV and Cu

Pillar Embedment for 1mm-Deep Fat TGV

(Tohoku University, T-Micro & Micro Technology)

Session 32: Solder and Through Via Interconnections: Material & Process Innovations

・Paper 7. Chemically-Tailored Cu Electroplating and Contactless Isostatic-Pressure Annealing of 1mm-Thick Full

Glass Wafer Cu Through-Glass Vias (Cu-TGVs)

(Tohoku University, T-Micro & JCU)

Session 39: Interactive Presentations Bonding Processes and Analysis in Next Generation Interconnects

・Paper 23. Reliable and Cost-Effective Fabrication of Low-Resistive and Void-Free Through-Glass Vias Using a

Reduction Gas-Generating Sinterable Cu Paste

(Tohoku University, T-Micro & Daicel)

３ハイブリッド接合 63件

Session 3: Advances in Low Temperature Hybrid Bonding

・Paper 1. Hybrid Bonding With Ultra-Low Temperature Annealing: Morphological and Electrical Validations

(Univ. Grenoble Alpes & CEA-LETI)

・Paper 2. Pressure-less Cu/Polymer Hybrid Bonding at Low Temperature and Fine Pitch Using a Novel Polymer

Adhesive with Precisely Controlled Composition

(Mitsui Chemicals & ASE)

・Paper 3. Reliable Low-Temperature (≤ 250°C) Cu/Dielectric Hybrid Bonding for High-Bandwidth Memory (HBM)

Stack Integration

(IME)

・Paper 4. Low-Temperature Chip Scale Cu-Cu Hybrid Bonding